SH7616 Datasheet, PDF (595/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR is set to 1.
The MPIE bit setting is invalid in synchronous mode and IrDA mode, and when the MP bit is 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1
Multiprocessor interrupts enabled^*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and
setting of the RDF and FER in SC1SSR and ORER in SC2SSR are disabled
until data with the multiprocessor bit set to 1 is received.
Note: * Receive data transfer from SCRSR to SCFRDR, receive error detection, and setting of the
RDF and FER in SC1SSR and ORER flags in SC2SSR, is not performed. When receive
data with MPB = 1 is received, the MPB flag in SC2SSR is set to 1, the MPIE bit is cleared
to 0 automatically, and generation of RXI and ERI (when the RIE bit in SCSCR is set to 1)
and FER and ORER flag setting is enabled.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCIF clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial
clock input pin. The function of the SCK pin should be selected with the pin function controller
(PFC).
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of
external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining
the SCIF’s operating mode with SCSMR.
For details of clock source selection, see table 14.9 in section 14.3, Operation.
Rev. 2.00 Mar 09, 2006 page 569 of 906
REJ09B0292-0200