SH7616 Datasheet, PDF (247/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
Break address mask register D (BAMRD) consists of two 16-bit readable/writable registers: break
address mask register DH (BAMRDH) and break address mask register DL (BAMRDL).
BAMRDH specifies which bits of the break address set in BARDH are to be masked, and
BAMRDL specifies which bits of the break address set in BARDL are to be masked. Operation
also depends on bits XYED and XYSD in BBRD as shown below.
BAMRD Configuration
XYED = 0
XYED = 1
Address
X address
(when XYSD = 0)
Y address
(when XYSD = 1)
Upper 16 Bits
(BAMD31 to BAMD16)
Upper 16 bits maskable
Maskable
—
Lower 16 Bits
(BAMD15 to BAMD0)
Lower 16 bits maskable
—
Maskable
Bit 31 to 0:
BAMDn
Description
0
Channel D break address bit BADn is included in break condition (Initial value)
1
Channel D break address bit BADn is masked, and not included in condition
Note: n = 31 to 0
Rev. 2.00 Mar 09, 2006 page 221 of 906
REJ09B0292-0200