SH7616 Datasheet, PDF (782/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 18 User Debug Interface (H-UDI)
Table 18.4 Instruction Configuration
Bit 15:
TS3
0
Bit 14:
TS2
0
Bit 13:
TS1
0
1
1
0
1
1
0
0
1
1
0
1
Bit 12:
TS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
EXTEST mode
Reserved
CLAMP mode
HIGHZ mode
SAMPLE/PRELOAD mode
Reserved
Reserved
Reserved
Reserved
Reserved
H-UDI interrupt
Reserved
Reserved
Reserved
IDCODE mode (Initial value)
BYPASS mode
Bits 11 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 756 of 906
REJ09B0292-0200