SH7616 Datasheet, PDF (120/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.33 Correspondence between DSP Instruction Operands and Registers
Register Sx
A0
Yes
A1
Yes
M0
—
M1
—
X0
Yes
X1
Yes
Y0
—
Y1
—
ALU and BPU Instructions
Sy
Dz
Du
—
Yes
Yes
—
Yes
Yes
Yes
Yes
—
Yes
Yes
—
—
Yes
Yes
—
Yes
—
Yes
Yes
Yes
Yes
Yes
—
Multiplication Instructions
Se
Sf
Dg
—
—
Yes
Yes
Yes
Yes
—
—
Yes
—
—
Yes
Yes
Yes
—
Yes
—
—
Yes
Yes
—
—
Yes
—
When writing parallel instructions, write the B field instructions first, then write the A field
instructions:
PADD A0,M0,A0 PMULS X0,Y0,M0
DCF PINC X1,A1
PCMP X1,M0
MOVX.W @R4+,X0
MOVX.W A0,@R5+R8
MOVX.W @R4+R8
MOVY.W @R6+,Y0[;]
MOVY.W @R7+,Y0[;]
[NOPY][;]
Text in brackets ([]) can be omitted. The no operation instructions NOPX and NOPY can be
omitted. Semicolons (;) are used to demarcate instruction lines, but can be omitted. If semicolons
are used, the space after the semicolon can be used for comments.
The individual status codes (DC, N, Z, V, GT) of the DSR register are always updated by
unconditional ALU operation instructions and shift operation instructions. Conditional instructions
do not update the status codes, even if the conditions have been met. Multiplication instructions
also do not update the status codes. DC bit definitions are determined by the specifications of the
CS bits in the DSR register.
Table 2.34 lists the DSP operation instructions by classification.
Rev. 2.00 Mar 09, 2006 page 94 of 906
REJ09B0292-0200