SH7616 Datasheet, PDF (806/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 18 User Debug Interface (H-UDI)
• SDIDR serial data input/output
In IDCODE mode, SDIDR is captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 31 of
SDIDR are output in that order from TDO.
In Update-DR, data input from TDI is not written to any register.
TDI
Shift register
Bit 31
Bit 15
.
.
SDIDR
..
SDIDR
Bit 0
Bit 0
TDO
Capture-DR
Figure 18.6 Serial Data Input/Output (3)
Rev. 2.00 Mar 09, 2006 page 780 of 906
REJ09B0292-0200