SH7616 Datasheet, PDF (102/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
The instruction codes, operation, and execution states of the CPU instructions are listed by
classification with the formats listed in below.
Instruction
Instruction Code
Operation
Execution
Cycles
T Bit
Indicated by mnemonic Indicated in MSB ↔
LSB order
Indicates summary of
operation
Explanation of Symbols Explanation of Symbols Explanation of Symbols
Value when Value of T bit
no wait
after
states are instruction is
inserted^*1 executed
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement^*2
mmmm: Source register →, ←: Transfer direction
nnnn: Destination register (xx): Memory operand
0000: R0
0001: R1
.........
M/Q/T: Flag bits in the SR
&: Logical AND of each bit
1111: R15
|: Logical OR of each bit
iiii: Immediate data
^: Exclusive OR of each bit
dddd: Displacement
~: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Explanation of
Symbols
—: No change
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums.
The actual number of cycles may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) and the register used by the next instruction are the
same.
2. Depending on the instruction’s operand size, scaling is ×1, ×2, or ×4. For details, see
the SH-1/SH-2/SH-DSP Software Manual.
Rev. 2.00 Mar 09, 2006 page 76 of 906
REJ09B0292-0200