SH7616 Datasheet, PDF (60/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits.
Status register (SR)
31 28 27
16 15 12 11 10 9 8 7
4 3 210
0000 RC 0000 DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S T
Repeat start register (RS)
31
0
RS
Repeat end register (RE)
31
0
RE
Global base register (GBR)
31
0
GBR
Vector base register (VBR)
31
0
VBR
Modulo register (MOD)
31
16 15
0
ME
MS
ME: Modulo end address
MS: Modulo start address
Figure 2.2 Control Register Configuration
Rev. 2.00 Mar 09, 2006 page 34 of 906
REJ09B0292-0200