SH7616 Datasheet, PDF (690/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Channel interrupt priority levels are set by means of the IRPE register, as described in section 5,
Interrupt Controller (INTC).
Table 15.3 SIOF Interrupt Sources
Interrupt Source Description
DMAC Activation Priority
RERI0
Receive overrun error (RERR)
Not possible
High
TERI0
RDFI0
TDEI0
Transmit underrun error (TERR)
Not possible
↑
Receive data register full (RDRF)/
Possible^*
↓
Receive Control Data Register Full (RCD)
Transmit data register empty (TDRE)/
Possible^*
Low
Transmit Control Data Register Empty (TCD)
Note: * The interrupt sources that can activate the DMAC are receive data full (RDRF) and transmit
data empty (TDRE).
It is not possible for receive control data full (RCD) or transmit control data empty (TCD) to
activate the DMAC.
The DMAC should be used to process RDRF and TDRE interrupts when using SIRCDR and
SITCDR, and the DMACE bit must be set to 1 in SICTR when using the CPU to process RCD
and TCD interrupts.
The DMACE bit should be cleared to 0 in SICTR if neither SIRCDR nor SITCDR is used and
both RDRF and TDRE interrupts as well as RCD and TCD interrupts are to be processed by
the CPU.
Rev. 2.00 Mar 09, 2006 page 664 of 906
REJ09B0292-0200