SH7616 Datasheet, PDF (24/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 18 User Debug Interface (H-UDI) .................................................................. 751
18.1 Overview........................................................................................................................... 751
18.1.1 Features................................................................................................................ 751
18.1.2 H-UDI Block Diagram......................................................................................... 752
18.1.3 Pin Configuration................................................................................................. 753
18.1.4 Register Configuration......................................................................................... 753
18.2 External Signals ................................................................................................................ 754
18.2.1 Test Clock (TCK) ................................................................................................ 754
18.2.2 Test Mode Select (TMS)...................................................................................... 754
18.2.3 Test Data Input (TDI) .......................................................................................... 754
18.2.4 Test Data Output (TDO) ...................................................................................... 755
18.2.5 Test Reset (TRST) ............................................................................................... 755
18.3 Register Descriptions ........................................................................................................ 755
18.3.1 Instruction Register (SDIR) ................................................................................. 755
18.3.2 Status Register (SDSR)........................................................................................ 757
18.3.3 Data Register (SDDR) ......................................................................................... 758
18.3.4 Bypass Register (SDBPR) ................................................................................... 758
18.3.5 Boundary scan register (SDBSR) ........................................................................ 758
18.3.6 ID code register (SDIDR) .................................................................................... 770
18.4 Operation .......................................................................................................................... 771
18.4.1 TAP Controller .................................................................................................... 771
18.4.2 H-UDI Interrupt and Serial Transfer.................................................................... 772
18.4.3 H-UDI Reset ........................................................................................................ 775
18.5 Boundary Scan .................................................................................................................. 775
18.5.1 Supported Instructions ......................................................................................... 775
18.5.2 Notes on Use........................................................................................................ 777
18.6 Usage Notes ...................................................................................................................... 777
Section 19 Pin Function Controller (PFC) ................................................................... 781
19.1 Overview........................................................................................................................... 781
19.2 Register Configuration...................................................................................................... 783
19.3 Register Descriptions ........................................................................................................ 783
19.3.1 Port A Control Register (PACR) ......................................................................... 783
19.3.2 Port A I/O Register (PAIOR)............................................................................... 786
19.3.3 Port B Control Registers (PBCR, PBCR2) .......................................................... 787
19.3.4 Port B I/O Register (PBIOR) ............................................................................... 793
Section 20 I/O Ports ............................................................................................................ 795
20.1 Overview........................................................................................................................... 795
20.2 Port A................................................................................................................................ 795
Rev. 2.00 Mar 09, 2006 page xxiv of xxvi