SH7616 Datasheet, PDF (399/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 8 Cache
To purge the cache using program logic, the data updates are detected by the program flow and the
cache is then purged. For example, if the program inputs data from a disk, whenever reading of a
unit (such as a sector) is completed, the buffer address used for reading or the entire cache is
purged, thereby maintaining coherency. When data is to be exchanged between two processors,
only flags that provide mutual notification of completion of data preparation or completion of a
fetch are placed in the cache-through area. The data actually to be transferred is placed in the
cache area and the cache is purged before the first data read to maintain the coherency of the data.
When semaphores are used as the means of communication, data coherency can be maintained
even when the cache is not purged by utilizing the TAS instruction. Direct external access must
always be used for a TAS instruction read.
When the update unit is small, specific addresses can be purged, so only the relevant addresses are
purged. When the update unit is larger, it is faster to purge the entire cache rather than purging all
the addresses in order, and then read the data that previously existed in the cache again from
external memory.
When write-back is used, coherency can be maintained by executing write-backs (flushing) to
memory by means of intentional cache miss reads, but since executing flushing incurs an
overhead, use of write-through or accessing the cache-through area is recommended in a system in
which a number of masters share memory.
8.5.4 Two-Way Cache Mode
The 4-kbyte cache can be used as 2-kbyte RAM and 2-kbyte mixed instruction/data cache memory
by setting the TW bit in CCR to 1. Ways 2 and 3 become cache, and ways 0 and 1 become RAM.
Initialization is performed by writing 1 to the CP bit in CCR, in the same way as with 4 ways. The
valid bit, and LRU bits are cleared to 0.
When LRU information is initialized to zero, the initial order of use is way 3 → way 2. Thereafter,
way 3 or way 2 is selected for replacement in accordance with the LRU information. The
conditions for updating the LRU information are the same as for four-way mode, except that the
number of ways is two.
When designated as 2-kbyte RAM, ways 0 and 1 are accessed by data array access. Figure 8.16
shows the address mapping.
Rev. 2.00 Mar 09, 2006 page 373 of 906
REJ09B0292-0200