SH7616 Datasheet, PDF (570/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 13 Watchdog Timer (WDT)
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the WDT.
ITI
(Interrupt
request signal)
WDTOVF
Internal
reset signal*
Interrupt
control
Overflow
Clock
Clock
select
Reset
control
φ/4
φ/128
φ/256
φ/512
φ/1024
φ/2048
φ/8192
φ/16384
Internal
clock
RSTCSR
WTCNT
WTCSR
Module bus
Bus
interface
WDT
φ: See figure 3.1, Block Diagram of Clock Pulse Generator Circuit.
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
RSTCSR: Reset control/status register
Note: * The internal reset signal can be generated by a register setting. The type of reset can
be selected (power-on or manual reset).
Figure 13.1 WDT Block Diagram
13.1.3 Pin Configuration
Table 13.1 shows the pin configuration.
Table 13.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
O
Function
Outputs the counter overflow signal in
watchdog timer mode
Rev. 2.00 Mar 09, 2006 page 544 of 906
REJ09B0292-0200