SH7616 Datasheet, PDF (417/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.10 Single Collision Detect Counter Register (SCDCR)
This register is a 32-bit counter that indicates the number of collisions on all lines from a start of
transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The
counter’s value is cleared to 0 by writing to this register. The value written is “don’t care”.
Bit: 31
30
29
28
27
26
25
24
COSDC31 COSDC30 COSDC29 COSDC28 COSDC27 COSDC26 COSDC25 COSDC24
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
COSDC23 COSDC22 COSDC21 COSDC20 COSDC19 COSDC18 COSDC17 COSDC16
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
COSDC15 COSDC14 COSDC13 COSDC12 COSDC11 COSDC10 COSDC9 COSDC8
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
COSDC7 COSDC6 COSDC5 COSDC4 COSDC3 COSDC2 COSDC1 COSDC0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 31 to 0–– Collision Detect Count 31 to 0 (COSDC31 to COSDC0): These bits indicate the
number of collisions from a start of transmission.
Rev. 2.00 Mar 09, 2006 page 391 of 906
REJ09B0292-0200