SH7616 Datasheet, PDF (348/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
Writing to address X + H'FFFF0000 or X + H'FFFF8000 first issues an all-bank precharge
command (PALL), then issues eight dummy auto-refresh commands (REF) required for the
synchronous DRAM power-on sequence. Lastly, a mode register write command (MRS) is issued.
Three idle cycles are inserted between the all-bank precharge command and the first auto-refresh
command, and eight idle cycles between auto-refresh commands, and between the eighth auto-
refresh command and the mode register write command, regardless of the MCR setting.
After writing to the synchronous DRAM mode register, perform a dummy read to each
synchronous DRAM bank before starting normal access. This will initialize the SH7616's internal
address comparator.
Synchronous DRAM requires a fixed idle time after powering on before the all-bank precharge
command is issued. Refer to the synchronous DRAM manual for the necessary idle time. When
the pulse width of the reset signal is longer than the idle time, the mode register may be set
immediately without problem. However, care is required if the pulse width of the reset signal is
shorter than the idle time.
Tp Tpw Tpw Tpw Trr Trc
CKIO
A24–A11
PALL
REF
A10
A9–A1
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
Trc Trr Trc
REF
Trc Tmw
MRS
Figure 7.36 Synchronous DRAM Mode Write Timing
Rev. 2.00 Mar 09, 2006 page 322 of 906
REJ09B0292-0200