SH7616 Datasheet, PDF (579/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 13 Watchdog Timer (WDT)
13.3.4 Timing of Overflow Flag (OVF) Setting
In interval timer mode, when WTCNT overflows, the OVF flag in WTCSR is set to 1 and an
interval timer interrupt (ITI) is requested (figure 13.6).
WTCNT
Overflow signal
(internal signal)
H'FF H'00
OVF
Figure 13.6 Timing of OVF Setting
13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting
When WTCNT overflows the WOVF flag in RSTCSR is set to 1 and a WDTOVF signal is output.
When the RSTE bit is set to 1, WTCNT overflow enables an internal reset signal to be generated
for the entire chip (figure 13.7).
WTCNT
Overflow signal
(internal signal)
WOVF
H'FF H'00
Figure 13.7 Timing of WOVF Setting
Rev. 2.00 Mar 09, 2006 page 553 of 906
REJ09B0292-0200