SH7616 Datasheet, PDF (252/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.2.18 Break Execution Times Register D (BETRD)
Bit: 15
14
13
12
11
10
9
8
—
—
—
— ETRD11 ETRD10 ETRD9 ETRD8
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
ETRD7
0
R/W
6
ETRD6
0
R/W
5
ETRD5
0
R/W
4
ETRD4
0
R/W
3
ETRD3
0
R/W
2
ETRD2
0
R/W
1
ETRD1
0
R/W
0
ETRD0
0
R/W
When a channel D execution-times break condition is enabled (by setting the ETBED bit in
BRCR), this 16-bit register specifies the number of times a channel D break condition occurs
before a user break interrupt is requested. The maximum value is 2¹² – 1 times. Each time a
channel D break condition occurs, the value in BETRD is decremented by 1. After the BETRD
value reaches H'0001, an interrupt is requested when a break condition next occurs.
As exceptions and interrupts cannot be accepted for instructions in a repeat loop comprising no
more than three instructions, BETRD is not decremented by the occurrence of a break condition
for an instruction in such a repeat loop (see 4.6, When Exception Sources Are Not Accepted).
Bits 15 to 12 are always read as 0, and should only be written with 0.
BETRD is initialized to H'0000 by a power-on reset.
Rev. 2.00 Mar 09, 2006 page 226 of 906
REJ09B0292-0200