SH7616 Datasheet, PDF (538/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Clock
Bus cycle
CPU
CPU
DMAC
HH
DMAC DMAC DMAC
HL
LH
LL
DREQn
(Active high)
1st
acceptance
Blind zone
Blind zone
2nd
acceptance
DACKn
(Active high)
DACK
HH
DACK DACK
HL
LH
DACK
LL
Figure 11.40 When an 8-Bit External Device is Connected (Level Detection)
DREQn Pin Input Detection Timing in Burst Mode: In burst mode, only edge detection is valid
for DREQn input. Operation is not guaranteed if level detection is set.
With edge detection of DREQn input, once a request is detected, DMA transfer continues until the
transfer end condition is satisfied, regardless of the state of the DREQn pin. Request detection is
not performed during this time. When the transfer start conditions are fulfilled after the end of
transfer, request detection is performed again every cycle.
Clock
Bus cycle
CPU
CPU
DMAC1
DMAC2
DMAC3
DMAC4
CPU
Bus DREQn
(Active high)
DACKn
(Active high)
Blind zone
Acceptance
Figure 11.41 DREQn Pin Input Detection Timing in Burst Mode with Edge Detection
Rev. 2.00 Mar 09, 2006 page 512 of 906
REJ09B0292-0200