SH7616 Datasheet, PDF (493/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
…
3
2
1
0
…
Initial value: —
—
—
…
—
—
—
—
R/W: R/W
R/W
R/W
…
R/W
R/W
R/W
R/W
DMA transfer count registers 0 and 1 (TCR0 and TCR1) are 32-bit read/write registers that
specify the DMA transfer count. The lower 24 of the 32 bits are valid. The value is written as 32
bits, including the upper eight bits. The number of transfers is 1 when the setting is H'00000001,
16,777,215 when the setting is H'00FFFFFF and 16, 777,216 (the maximum) when H'00000000 is
set. During a DMA transfer, these registers indicate the remaining transfer count.
Set the initial value as the write value in the upper eight bits. These bits always read 0. Values are
retained in a reset, in standby mode, and when the module standby function is used. For 16-byte
transfers, set the count to 4 times the number of transfers. Operation is not guaranteed if an
incorrect value is set.
11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1)
Bit: 31
30
29
…
19
18
17
16
—
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
DM1 DM0 SM1 SM0
TS1
TS0
AR
AM
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
AL
DS
DL
Initial value: 0
0
0
R/W: R/W
R/W
R/W
Note: Only 0 can be written, to clear the flag.
4
3
2
1
0
TB
TA
IE
TE
DE
0
0
0
0
0
R/W
R/W
R/W _R/(W)* R/W
Rev. 2.00 Mar 09, 2006 page 467 of 906
REJ09B0292-0200