SH7616 Datasheet, PDF (152/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 4 Exception Handling
Table 4.1 Types of Exception Handling and Priority Order
Exception Source
Priority
Reset
Power-on reset
High
Manual reset
↑
Address
error
CPU address error
DMA address error (DMAC and E-DMAC)
Interrupt NMI
User break
User debug interface (H-UDI)
External interrupts (IRL1–IRL15, IRQ0–IRQ3 (set with IRL3, IRL2, IRL1,
IRL0 pins))
On-chip peripheral modules Direct memory access controller (DMAC)
Watchdog timer (WDT)
Compare match interrupt (part of the bus
state controller)
Ethernet controller (EtherC) and Ethernet
controller direct memory access controller
(E-DMAC)
16-bit free-running timer (FRT)
Serial communication interface with FIFO
(SCIF)
16-bit timer pulse unit (TPU)
Serial I/O with FIFO (SIOF)
Serial I/O (SIO)
Instructions Trap instruction (TRAPA)
General illegal instructions (undefined code)
↓
Illegal slot instructions (undefined code placed directly following a delayed Low
branch instruction^*1 or instructions that rewrite the PC^*2)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
Rev. 2.00 Mar 09, 2006 page 126 of 906
REJ09B0292-0200