SH7616 Datasheet, PDF (371/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.9 Bus Arbitration
The chip has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device after the bus cycle being executed is completed.
The chip keeps the bus under normal conditions and permits other devices to use the bus by
releasing it when they request its use.
In the following explanation, external devices requesting the bus are called slaves.
The chip has three internal bus masters, the CPU, the DMAC and the E-DMAC. When
synchronous DRAM or DRAM is connected and refresh control is performed, the refresh request
becomes a fourth master. In addition to these, there are also bus requests from external devices.
The priority for bus requests when they occur simultaneously is as follows.
Refresh request External device E-DMAC DMAC CPU
However, only one E-DMAC channel can hold the bus during one bus-mastership cycle.
The E-DMAC has two channels to handle both transmission and reception. Arbitration between
the channels is performed automatically within the E-DMAC module, with bus mastership
alternating between the transmit channel and the receive channel. For arbitration between the two
DMAC channels, either fixed priority mode or round robin mode can be selected by means of the
priority mode bit (PR) in the DMA operation register (DMAOR).
When the bus is being passed between slave and master, all bus control signals are negated before
the bus is released to prevent erroneous operation of the connected devices. When the bus is
transferred, also, the bus control signals begin bus driving from the negated state. The master and
slave passing the bus between them drive the same signal values, so output buffer conflict is
avoided. A pull-up resistance is required for the bus control signals to prevent malfunction caused
by external noise when they are at high impedance.
Bus permission is granted at the end of the bus cycle. When the bus is requested, the bus is
released immediately if there is no ongoing bus cycle. If there is a current bus cycle, the bus is not
released until the bus cycle ends. Even when a bus cycle does not appear to be in progress when
viewed from off-chip, it is not possible to determine immediately whether the bus has been
released by looking at CSn or other control signals, since a bus cycle (such as wait insertion
between access cycles) may have been started internally. The bus cannot be released during burst
transfers for cache filling, DMAC 16-byte block transfers (16 + 16 = 32-byte transfers in dual
address mode), or E-DMAC 16-byte block transfers. Likewise, the bus cannot be released between
the read and write cycles of a TAS instruction. Arbitration is also not performed between multiple
Rev. 2.00 Mar 09, 2006 page 345 of 906
REJ09B0292-0200