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SH7616 Datasheet, PDF (276/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
Section 7 Bus State Controller (BSC)
 Selection of burst read, single write mode or burst read, burst write mode
 Bank active mode
• Bus arbitration
 All resources are shared with the CPU, and use of the bus is granted on reception of a bus
release request from off-chip.
• Refresh counter can be used as an interval timer
 Interrupt request generation on compare match (CMI interrupt request signal).
Rev. 2.00 Mar 09, 2006 page 250 of 906
REJ09B0292-0200