SH7616 Datasheet, PDF (193/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
Bits 6 to 0—16-Bit Free-Running Timer (FRT) Output-Compare Interrupt Vector Number 6 to 0
(FOCV6–FOCV0): These bits set the vector number for the 16-bit free-running timer (FRT)
output-compare interrupt (OCI). There are seven bits, so the value can be set between 0 and 127.
5.3.10 Vector Number Setting Register D (VCRD)
Vector number setting register D (VCRD) is a 16-bit read/write register that sets the 16-bit free-
running timer (FRT) overflow interrupt vector number (0–127). VCRD is initialized to H'0000 by
a reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
— FOVV6 FOVV5 FOVV4 FOVV3 FOVV2 FOVV1 FOVV0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 and 7 to 0—Reserved: These bits are always read as 0. The write value should always be
0.
Bits 14 to 8—16-Bit Free-Running Timer (FRT) Overflow Interrupt Vector Number 6 to 0
(FOVV6–FOVV0): These bits set the vector number for the 16-bit free-running timer (FRT)
overflow interrupt (OVI). There are seven bits, so the value can be set between 0 and 127.
Rev. 2.00 Mar 09, 2006 page 167 of 906
REJ09B0292-0200