SH7616 Datasheet, PDF (323/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
output cycle Tc and the initial read data fetch cycle Td1 can be specified between 1 cycle and 4
cycles using the W21/W20 and W31/W30 bits in WCR1. The number of cycles at this time
corresponds to the number of CAS latency cycles of the synchronous DRAM. When 2 cycles or
more, a NOP command issue cycle Tw is inserted between the Tc cycle and the Td1 cycle. The
number of cycles in the precharge completion waiting cycle Tap is specified by bits TRP1 and
TRP0 in MCR. When CAS latency is 1, a Tap cycle comprising the number of cycles specified by
TRP1 and TRP0 is generated. When the CAS latency is 2 or more, a Tap cycle equal to the TRP
specification – 1 is generated. During the Tap cycle, no commands other than NOP are issued to
the same bank. Figure 7.23 (a) and (b) show examples of burst read timing when RCD1/RCD0 is
01, W31/W30 is 01, and TRP1/TRP0 is 01.
When the data width is 16 bits, 8 burst cycles are required for a 16-byte data transfer. The data
fetch cycle goes from Td1 to Td8.
Synchronous DRAM CAS latency is up to 3 cycles, but the CAS latency of the bus state controller
can be specified up to 4. This is so that circuits containing latches can be installed between
synchronous DRAMs and the chip.
Tr
CKIO
A24–A11
A10
A9–A1
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31–D0
DACKn*
Tc
Td1
Td2
Td3
Td4
Tde
Tap
Note: * DACKn waveform when active-low is specified.
Figure 7.22 (a) Basic Burst Read Timing (Auto-Precharge) Iφ : Eφ other than 1 : 1
Rev. 2.00 Mar 09, 2006 page 297 of 906
REJ09B0292-0200