SH7616 Datasheet, PDF (702/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 16 Serial I/O (SIO)
16.3.2 Output
Figure 16.4 shows interval transfer mode (SE set to 1 in SICTR) when TM is cleared to 0 in
SICTR.
Figure 16.5 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is cleared to 0
in SICTR.
Figure 16.6 shows interval transfer mode (SE set to 1 in SICTR) when TM is set to 1 in SICTR.
Figure 16.7 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is set to 1 in
SICTR.
TDRE
synchronous internal clock
SITDR
Data C
SITSR
Undefined
C[7:0] C[6:0] C[5:0]
C[0]
D[7:0] D[6:0]
STCK
STS
STxD
C[7] C[6] C[5] C[1] C[0]
Invalid
D[7]
Notes: TM = 0: STS is input
DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
Figure 16.4 Transmission: Interval Transfer Mode (TM = 0 Mode)
Rev. 2.00 Mar 09, 2006 page 676 of 906
REJ09B0292-0200