SH7616 Datasheet, PDF (732/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for
TCNT.
Bit n: CSTn
Description
0
TCNTn count operation is stopped
(Initial value)
1
TCNTn performs count operation
Note:
n = 2 to 0
If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops, but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
17.2.9 Timer Synchronous Register (TSYR)
Bit: 7
6
5
4
—
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
3
2
1
0
— SYNC2 SYNC1 SYNC0
0
0
0
0
R
R/W R/W R/W
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset.
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 2 to 0—Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*¹, and
synchronous clearing through counter clearing on another channel*² are possible.
Bit n: SYNCn Description
0
TCNTn operates independently
(Initial value)
TCNT presetting/clearing is unrelated to other channels
1
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
Notes: n = 2 to 0
1. To set synchronous operation, the SYNC bits for two channels at least must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
Rev. 2.00 Mar 09, 2006 page 706 of 906
REJ09B0292-0200