SH7616 Datasheet, PDF (592/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Bit 3—Stop Bit Length (STOP)/IrDA Clock Select 0 (ICK0): Selects 1 or 2 bits as the stop bit
length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When
synchronous mode is set, the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP
Description
0
1 stop bit^*1
(Initial value)
1
2 stop bits^*2
Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
In IrDA communication mode, bit 3 is the IrDA clock select 0 (ICK0) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only
valid in asynchronous mode; it is invalid in synchronous mode and IrDA mode.
For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor
Communication Function.
Bit 2: MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the built-
in baud rate generator. The clock source can be selected from Pφ, Pφ/4, Pφ/16, and Pφ/64,
according to the setting of bits CKS1 and CKS0.
Rev. 2.00 Mar 09, 2006 page 566 of 906
REJ09B0292-0200