SH7616 Datasheet, PDF (238/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
BARC Configuration
Upper 16 Bits
(BAC31 to BAC16)
Lower 16 Bits
(BAC15 to BAC0)
XYEC = 0 Address
Upper 16 bits of address bus Lower 16 bits of address bus
XYEC = 1 X address
X address
—
(when XYSC = 0) (XAB15 to XAB1)^*
Y address
—
(when XYSC = 1)
Y address
(YAB15 to YAB1)^*
Note: * As an X/Y bus access is always a word access, the values of XAB0 and YAB0 is not
included in the break condition.
6.2.8 Break Address Mask Register C (BAMRC)
BAMRCH
Bit: 15
14
13
12
11
10
9
8
BAMC31 BAMC30 BAMC29 BAMC28 BAMC27 BAMC26 BAMC25 BAMC24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
BAMC23 BAMC22 BAMC21 BAMC20 BAMC19 BAMC18 BAMC17 BAMC16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BAMRCL
Bit: 15
14
13
12
11
10
9
8
BAMC15 BAMC14 BAMC13 BAMC12 BAMC11 BAMC10 BAMC9 BAMC8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
BAMC7
0
R/W
6
BAMC6
0
R/W
5
BAMC5
0
R/W
4
BAMC4
0
R/W
3
BAMC3
0
R/W
2
BAMC2
0
R/W
1
BAMC1
0
R/W
0
BAMC0
0
R/W
Rev. 2.00 Mar 09, 2006 page 212 of 906
REJ09B0292-0200