SH7616 Datasheet, PDF (486/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
1), this indicates a buffer for which reception has not yet been performed. If a frame receive error
occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted
immediately and a status write-back to the descriptor is performed.
If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register
(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame
receive request, reception is continued from the buffer after that in which the error occurred.
Descriptors
E-DMAC
Inactivates RACT and writes RFE, RFS
Descriptor read
:
:
:
:
:
Write-back
00 10
00 00
00 00
00 00
10 00
10 00
10 00
10 00
11 00
Start of frame
Receive error occurrence
New frame reception
continues from this buffer
Buffer
Figure 10.7 E-DMAC Operation after Receive Error
Received data
Unreceived data
Rev. 2.00 Mar 09, 2006 page 460 of 906
REJ09B0292-0200