SH7616 Datasheet, PDF (480/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Note: This bit is set to 1 when any of Receive Frame Status bit 9, bit 7, bits 4 to 0 is set.
When this bit is set, the Receive Frame Error bit (bit 27: RFE) is set to 1.
• RFS7—Receive Multicast Address Frame (corresponds to RMAF bit in EESR)
• RFS6—Reserved*¹
• RSF5— Receive Frame Discard Request Assertion (corresponds to RFAR bit in EESR)*¹
• RFS4—Receive Residual-Bit Frame (corresponds to RRF bit in EESR)
• RFS3—Receive Too-Long Frame (corresponds to RTLF bit in EESR)
• RFS2—Receive Too-Short Frame (corresponds to RTSF bit in EESR)
• RFS1—PHY-LSI Receive Error (corresponds to PRE bit in EESR)
• RFS0—CRC Error on Received Frame (corresponds to CERF bit in EESR)
Note: 1. Only HD6417616 is effective. HD6417615 is Reserved bit.
Receive Descriptor 1 (RD1): Specifies the receive buffer length (maximum 64 kbytes).
Bits 31 to 16—Receive Buffer Length (RBL): These bits specify the maximum transfer byte
length in the corresponding receive buffer.
Notes: The transfer byte length must align with a 16-byte boundary (bits 19 to 16 cleared to 0).
The maximum receive frame length with one frame per buffer is 1,514 bytes, excluding
the CRC data. Therefore, for the receive buffer length specification, a value of 1,520 bytes
(H'05F0) that takes account of a 16-byte boundary is set as the maximum receive frame
length.
Bits 15 to 0—Receive Data Length (RDL): These bits specify the data length of a receive frame
stored in the receive buffer.
Note: The receive data transferred to the receive buffer does not include the 4-byte CRC data at
the end of the frame. The receive frame length is reported as the number of words (valid
data bytes) not including this CRC data.
Receive Descriptor 2 (RD2): Specifies the 32-bit receive buffer start address.
Note: The receive buffer’s start address setting must be aligned with a longword boundary.
However, when SDRAM is connected, the setting must be aligned with a 16-byte
boundary.
Bits 31 to 0—Receive Buffer Address (RBA)
Rev. 2.00 Mar 09, 2006 page 454 of 906
REJ09B0292-0200