SH7616 Datasheet, PDF (528/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
When external memory is set as bank active synchronous DRAM, during a single read the
acknowledge signal is output across the read command, wait and read address when the row
address is the same as the previous address output (figure 11.24). When the row address is
different from the previous address, the acknowledge signal is output across the precharge, row
address, read command, wait and read address (figure 11.25). Since the synchronous DRAM read
has only burst mode, during a single read an invalid address is output; the acknowledge signal is
output on the same timing. At this time, the acknowledge signal is extended until the write address
is output after the invalid read.
Clock
DACKn
(Active high)
Address
bus
CPU
Read
command
Read
Invalid read
Row Column
address address
DMAC read (basic timing)
DMAC write (basic timing)
Figure 11.24 DACKn Output in Synchronous DRAM Single Read
(Bank Active, Same Row Address, AM = 0)
Clock
DACKn
(Active high)
Address
bus
CPU
Row
address
Pre-
Read
charge command Read
Invalid read
Row Column
address address
DMAC read
(basic timing)
DMAC write
(basic timing)
Figure 11.25 DACKn Output in Synchronous DRAM Single Read
(Bank Active, Different Row Address, AM = 0)
Rev. 2.00 Mar 09, 2006 page 502 of 906
REJ09B0292-0200