SH7616 Datasheet, PDF (303/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused
by the CMF bit of RTCSR when CMF is set to 1.
Bit 6: CMIE
0
1
Description
Interrupt request caused by CMF is disabled
Interrupt request caused by CMF is enabled
(Initial value)
Bits 5 to 3—Clock Select Bits (CKS2–CKS0)
Bit 5: CKS2
0
1
Bit 4: CKS1
0
1
0
1
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
Count-up disabled
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/2048
Pφ/4096
(Initial value)
Bits 2 to 0—Refresh Count (RRC2–RRC0): These bits specify the number of consecutive
refreshes to be performed when the refresh timer counter (RTCNT) and refresh time constant
register (RTCOR) values match and a refresh request is issued.
Bit 2: RRC2
0
1
Bit 1: RRC1
0
1
0
1
Bit 0: RRC0
0
1
0
1
0
1
0
1
Description
1 refresh
2 refreshes
4 refreshes
6 refreshes
8 refreshes
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
(Initial value)
Rev. 2.00 Mar 09, 2006 page 277 of 906
REJ09B0292-0200