SH7616 Datasheet, PDF (279/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
Signal
With Bus
I/O Released Description
DREQ1 I I
DMA request 1
DACK1 O O
DMA acknowledge 1
REFOUT O O
Refresh execution request output when bus is released
DQMUU/ O Hi-Z
WE3
When synchronous DRAM is used, connected to DQM pin for the
most significant byte (D31–D24). For ordinary space, indicates
writing to the most significant byte
DQMUL/ O Hi-Z
WE2
When synchronous DRAM is used, connected to DQM pin for the
second byte (D23–D16). For ordinary space, indicates writing to the
second byte
DQMLU/ O Hi-Z
WE1
When synchronous DRAM is used, connected to DQM pin for the
third byte (D15–D8). For ordinary space, indicates writing to the
third byte
DQMLL/ O Hi-Z
WE0
When synchronous DRAM is used, connected to DQM pin for the
least significant byte (D7–D0). For ordinary space, indicates writing
to the least significant byte
CAS3
O Hi-Z
When DRAM is used, connected to CAS pin for the most significant
byte (D31–D24)
CAS2
O Hi-Z
When DRAM is used, connected to CAS pin for the second byte
(D23–D16)
CAS1
O Hi-Z
When DRAM is used, connected to CAS pin for the third byte (D15–
D8)
CAS0
O Hi-Z
When DRAM is used, connected to CAS pin for the least significant
byte (D7–D0)
STATS0, 1 O O
Bus master identification
00: CPU
01: DMAC
10: E-DMAC
11: Other
BUSHIZ I I
Signal used in combination with WAIT signal to place bus and
strobe signals in the high-impedance state without the ending bus
cycle.
Note: Hi-Z: High impedance
Rev. 2.00 Mar 09, 2006 page 253 of 906
REJ09B0292-0200