SH7616 Datasheet, PDF (644/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Transfer
direction
Serial clock
Serial data
LSB
Bit 0
Bit 1
MSB
Bit 7
Bit 0
Bit 1
Bit 6 Bit 7
TDFE
TEND
TXI interrupt
request
Data written to SCFTDR
and TDFE flag cleared
to 0 by TXI interrupt
handler
One frame
TXI interrupt
request
Figure 14.19 Example of SCIF Transmit Operation (Example of LSB-First Transfer)
• Serial Data Reception (Synchronous Mode)
Figure 14.20 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When changing the operating mode from asynchronous to synchronous without resetting
SCFRDR and SCFTDR by means of SCIF initialization, be sure to check that the ORER,
PER3 to PER0, and FER3 to FER0 flags are all cleared to 0. The RDF flag will not be set if
any of flags FER3 to FER0 or PER3 to PER0 are set to 1, and neither transmit nor receive
operations will be possible.
Rev. 2.00 Mar 09, 2006 page 618 of 906
REJ09B0292-0200