SH7616 Datasheet, PDF (772/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 17.50 shows the timing in this case.
Pφ
Address
TGR write cycle
T1
T2
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 17.50 Contention between TGR Write and Input Capture
Rev. 2.00 Mar 09, 2006 page 746 of 906
REJ09B0292-0200