SH7616 Datasheet, PDF (524/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Clock
DACKn
(Active high)
Address
bus
CPU H
Invalid
*¹
*² write
DMAC read H DMAC read L
DMAC write
Basic timing
Notes: 1. H: MSB side
2. L: LSB side
Figure 11.16 DACKn Output in Ordinary Space Accesses
(AM = 0, Longword Access to 16-Bit External Device)
Clock
DACKn
(Active high)
Address
bus
CPU
DMAC
read HH
DMAC
read HL
DMAC
read LH
DMAC
read LL
Basic timing
Figure 11.17 DACKn Output in Ordinary Space Accesses
(AM = 0, Longword Access to 8-Bit External Device)
Clock
DACKn
(Active high)
Address
bus
CPU
Invalid
write
DMAC read H DMAC read L
DMAC write
Basic timing
Figure 11.18 DACKn Output in Ordinary Space Accesses
(AM = 0, Word Access to 8-Bit External Device)
Rev. 2.00 Mar 09, 2006 page 498 of 906
REJ09B0292-0200