SH7616 Datasheet, PDF (668/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
with a value less than or equal to the setting of TFWM3 to TFWM0 in SIFCR is transferred from
SITDR to SITSR, TDRE is set in SISTR. If at this point the transmit interrupt enable flag (TIE) is
set, a transmit-data-empty interrupt (TDEI) request is sent to the INTC and DMAC. If TIE is
cleared, this interrupt request is not generated. When the DMAC writes to SITDR data with a
value greater than the setting of TFWM3 to TFWM0 in SIFCR, the TDRE flag is cleared
automatically. The TDRE flag is set only by hardware.
When SITDR is reset, its status is empty. The status of SITDR is also empty when the value of the
transmit FIFO data registry reset bit (TFRST) in SITDR is 1.
Note:
Do not write to SITDR when it is full of primary transmit data (when the value of the
transmit data register data count bits 4 to 0 (T4 to T0) in SIFDR is 10000).
Data should be written to SITDR in the size specified by the setting of the DL bit in
SICTR. Always set the TE bit to 1 before writing to this register.
15.2.5 Serial Control Register (SICTR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
— DMACE TCIE RCIE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
TM
SE
DL
TIE
RIE
TE
RE
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
SICTR is a 16-bit register used to set parameters for serial port control. SICTR is initialized to
H'0000 by a reset.
When modifying bit 4, 5, 6,or 10 (DMACE, TM, SE, or DL), TE and RE (bit 1, 0) should be
cleared to 0 beforehand.
Bits 15 to 11—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 10—DMAC Activation Enable (DMACE): Specifies whether the DMAC is activated by
interrupts triggered by the RDRF and TDRE bits in SISTR.
Set this bit to 1 if SIRCDR and SITCDR are used. This will cause interrupts triggered by the
RDRF and TDRE bits in SISTR to be processed by the DMAC and interrupts triggered by the
RCD and TCD bits in SISTR to be processed by the CPU.
Rev. 2.00 Mar 09, 2006 page 642 of 906
REJ09B0292-0200