SH7616 Datasheet, PDF (430/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
Note: If a collision or the carrier-not-detected state occurs during data transmission, these are
reported as interrupt sources.
4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is
more transmit data, continues transmitting.
9.3.2 Reception
The EtherC receiver separates a received frame into preamble, SFD, data, and CRC, and the fields
from DA (destination address) to the CRC data are transferred to the receive E-DMAC. The main
receive functions of the EtherC are as follows:
• Receive frame header check: Checks the preamble and SFD, and discards a frame with an
invalid pattern
• Receive frame data check: Checks the data length in the header, and reports an error status if
the data length is less than 64 bytes or greater than the specified number of bytes
• Receive CRC check: Performs a CRC check on the frame data field, and reports an error status
in the case of an abnormality
• Line status monitoring: Reports an error status if an illegal carrier is detected by means of the
fault detection signal from the PHY-LSI
• Magic Packet monitoring: Detects a Magic Packet from all receive frames
The state transitions of the EtherC receiver are shown in figure 9.3.
Rev. 2.00 Mar 09, 2006 page 404 of 906
REJ09B0292-0200