SH7616 Datasheet, PDF (230/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.2.2 Break Address Mask Register A (BAMRA)
BAMRAH
Bit: 15
14
13
12
11
10
9
8
BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BAMRAL
Bit: 15
14
13
12
11
10
9
BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9
Initial value: 0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
BAMA8
0
R/W
Bit:
Initial value:
R/W:
7
BAMA7
0
R/W
6
BAMA6
0
R/W
5
BAMA5
0
R/W
4
BAMA4
0
R/W
3
BAMA3
0
R/W
2
BAMA2
0
R/W
1
BAMA1
0
R/W
0
BAMA0
0
R/W
Break address mask register A (BAMRA) consists of two 16-bit readable/writable registers: break
address mask register AH (BAMRAH) and break address mask register AL (BAMRAL).
BAMRAH specifies which bits of the break address set in BARAH are to be masked, and
BAMRAL specifies which bits of the break address set in BARAL are to be masked. BAMRAH
and BAMRAL are initialized to H'0000 by a power-on reset; after a manual reset, their values are
undefined.
BAMRAH Bits 15 to 0—Break Address Mask A31 to A16 (BAMA31 to BAMA16): These bits
specify whether or not corresponding channel A break address bits 31 to 16 (BAA31 to BAA16)
set in BARAH are to be masked.
Rev. 2.00 Mar 09, 2006 page 204 of 906
REJ09B0292-0200