SH7616 Datasheet, PDF (186/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.3.2 Interrupt Priority Level Setting Register B (IPRB)
Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority
levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 by a
reset. It is not initialized in standby mode.
Bit: 15
14
13
12
E-DMAC E-DMAC E-DMAC E-DMAC
IP3
IP2
IP1
IP0
Initial value:
0
0
0
0
R/W: R/W
R/W
R/W
R/W
11
FRTIP3
0
R/W
10
FRTIP2
0
R/W
9
FRTIP1
0
R/W
8
FRTIP0
0
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 to 12—Ethernet Controller Direct Memory Access Controller (E-DMAC) Interrupt
Priority Level 3 to 0 (E-DMACIP3–E-DMACIP0): These bits set the ethernet controller direct
memory access controller (E-DMAC) interrupt priority level. There are four bits, so levels 0–15
can be set.
Bits 11 to 8—16-Bit Free-Running Timer (FRT) Interrupt Priority Level 3 to 0 (FRTIP3–
FRTIP0): These bits set the 16-bit free-running timer (FRT) interrupt priority level. There are four
bits, so levels 0–15 can be set.
Bits 7 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 160 of 906
REJ09B0292-0200