SH7616 Datasheet, PDF (103/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.20 Data Transfer Instructions
Instruction
MOV #imm,Rn
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV Rm,Rn
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L Rm,@–Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L @(disp,Rm),Rn
MOV.B Rm,@(R0,Rn)
MOV.W Rm,@(R0,Rn)
Instruction Code
Operation
1110nnnniiiiiiii imm → Sign extension →
Rn
1001nnnndddddddd (disp × 2 + PC) → Sign
extension → Rn
1101nnnndddddddd (disp × 4 + PC) → Rn
0110nnnnmmmm0011 Rm → Rn
0010nnnnmmmm0000 Rm → (Rn)
0010nnnnmmmm0001 Rm → (Rn)
0010nnnnmmmm0010 Rm → (Rn)
0110nnnnmmmm0000 (Rm) → Sign extension →
Rn
0110nnnnmmmm0001 (Rm) → Sign extension →
Rn
0110nnnnmmmm0010 (Rm) → Rn
0010nnnnmmmm0100 Rn–1 → Rn, Rm → (Rn)
0010nnnnmmmm0101 Rn–2 → Rn, Rm → (Rn)
0010nnnnmmmm0110 Rn–4 → Rn, Rm → (Rn)
0110nnnnmmmm0100 (Rm) → Sign extension →
Rn,Rm + 1 → Rm
0110nnnnmmmm0101 (Rm) → Sign extension →
Rn,Rm + 2 → Rm
0110nnnnmmmm0110 (Rm) → Rn,Rm + 4 → Rm
10000000nnnndddd R0 → (disp + Rn)
10000001nnnndddd R0 → (disp × 2 + Rn)
0001nnnnmmmmdddd Rm → (disp × 4 + Rn)
10000100mmmmdddd (disp + Rm) → Sign
extension → R0
10000101mmmmdddd (disp × 2 + Rm) → Sign
extension → R0
0101nnnnmmmmdddd (disp × 4 + Rm) → Rn
0000nnnnmmmm0100 Rm → (R0 + Rn)
0000nnnnmmmm0101 Rm → (R0 + Rn)
Cycles
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T Bit
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Rev. 2.00 Mar 09, 2006 page 77 of 906
REJ09B0292-0200