SH7616 Datasheet, PDF (439/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.3.7 CAM Match Signal Input Function
The EtherC is equipped with a CAM (Content Addressable Memory) match signal input function.
A CAM circuit is externally connected to compare a destination address in a receive frame (see
figure 9.7). The EtherC receives the result of comparison of a destination address corresponding to
signals (RXD3 to RXD0) fetched from the MII as a signal from a CAMSEN pin and selects
whether the current frame is received or discarded.
SH7616
EtherC
MII (RX-DV, RXD3 to RXD0) _PHY-LSI
CAMSEN
CAM logic
Figure 9.7 CAM Circuit Connection
Table 9.3 shows types of frames received and discarded in the two states of the CAMSEN signal.
The CAM holds the MAC address besides this LSI. When the MAC address which is received
from the PHY-LSI is matched with the destination address held in the CAM, the CAMSEN signal
is asserted. The EtherC recognizes that the CAMSEN signal has been asserted then receives a
frame for the reception.
Some of the frame’s data will have already been stored in the receive FIFO when the CAMSEN
signal is asserted. Therefore, when the E-DMAC is requested that the received data be discarded,
the E-DMAC discards the frame. The frame must be discarded before DMA transfer starts because
the E-DMAC starts transferring to main memory by DMA when at least 16 bytes of data is stored
in the receive FIFO. In this case, according to the MII receive signal timing, the RX-DV is
asserted and the CAMSEN signal must be asserted within 35 clock cycles of the start timing of a
Rev. 2.00 Mar 09, 2006 page 413 of 906
REJ09B0292-0200