SH7616 Datasheet, PDF (376/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
CKIO
BRLS
BGR
Address data
CSn
Other bus
control signals
Figure 7.58 Bus Arbitration
7.10 Additional Items
7.10.1 Resets
The bus state controller is completely initialized only in a power-on reset. All signals are
immediately negated, regardless of whether or not the chip is in the middle of a bus cycle. Signal
negation is simultaneous with turning the output buffer off. All control registers are initialized. In
standby mode, sleep mode, and a manual reset, no bus state controller control registers are
initialized. When a manual reset is performed, the currently executing bus cycle only is completed,
and then the chip waits for an access. When a cache-filling or DMAC/E-DMAC 16-byte transfer is
executing, the CPU, DMAC, or E-DMAC that is the bus master ends the access in a longword
unit, since the access request is canceled by the manual reset.This means that when a manual reset
is executed during a cache filling, the cache contents can no longer be guaranteed. During a
manual reset, the RTCNT does not count up, so no refresh request is generated, and a refresh cycle
is not initiated. To preserve the data of the DRAM and synchronous DRAM, the pulse width of the
manual reset must be shorter than the refresh interval.
The bus-release operation of this LSI during a manual reset is described below.
• BRLS signal is asserted before transition to manual reset state and continues to be asserted
during manual reset
In this LSI, the BGR signal is continuously asserted to retain the bus-release state.
• BRLS signal is asserted before transition to manual reset state and negated during manual reset
In this LSI, the BGR signal is negated to acquire the bus.
• BRLS signal is asserted during manual reset
In this LSI, the BGR signal is not asserted until the manual reset is released.
Rev. 2.00 Mar 09, 2006 page 350 of 906
REJ09B0292-0200