SH7616 Datasheet, PDF (834/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 21 Power-Down Modes
Oscillator
CKIO
(output)
NMI
NMIE
SBY
NMI
exception
handling
Exception
service routine,
SBY = 1,
SLEEP instruction
Standby mode
Oscillation
settling time
WDT
set time
Start of
oscillation
NMI exception
handling
Figure 21.1 Standby Mode Cancellation by NMI Interrupt
21.4.4 Clock Pause Function
When the clock is input from the CKIO pin, the clock frequency can be modified or the clock
stopped. The CKPREQ/CKM pin is provided for this purpose. Note that clock pauses are not
accepted while the watchdog timer (WDT) is operating (i.e. when the timer enable bit (TME) in
the WDT’s timer control/status register (WTCSR) is 1). When the clock pause request function is
used, the standby bit (SBY) in the standby control register 1 (SBYCR1) must be set to 1 before
inputting the request signal. The clock pause function is used as described below.
1. Set the TME bit in the watchdog timer’s WTCSR register to 0, and set the SBY bit in
SBYCR1 to 1.
2. Apply a low level to the CKPREQ/CKM pin.
3. When the chip enters the standby state internally, a low level is output from the CKPACK pin.
4. After confirming that the CKPACK pin has gone low, perform clock halting or frequency
modification.
5. To cancel the clock pause state (standby state), apply a high level to the CKPREQ/CKM pin.
(Inside the chip , the standby state is canceled by detecting a rising edge at the CKPREQ/CKM
pin.)
Rev. 2.00 Mar 09, 2006 page 808 of 906
REJ09B0292-0200