SH7616 Datasheet, PDF (91/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Instruction Formats
Destination
Source Operand Operand
Example
d format
15
xxxx xxxx
0
dddd dddd
dddddddd: Indirect R0 (Direct register) MOV.L
GBR with
@(disp,GBR),R0
displacement
R0(Direct register) dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
displacement
dddddddd: PC
relative
R0 (Direct register) MOVA
@(disp,PC),R0
—
BF label
d12 format
15
xxxx dddd
dddd
0
dddd
dddddddddddd: —
PC relative
BRA label
(label=disp+PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
i format
iiiiiiii:
Immediate
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
15
0
xxxx xxxx i i i i i i i i
iiiiiiii:
Immediate
R0 (Direct register) AND #imm,R0
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii:
Immediate
iiiiiiii:
Immediate
—
nnnn: Direct
register
TRAPA #imm
ADD #imm,Rn
Note: * In multiply/accumulate instructions, nnnn is the source register.
Rev. 2.00 Mar 09, 2006 page 65 of 906
REJ09B0292-0200