SH7616 Datasheet, PDF (678/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Bit 3 to 0— Transmit FIFO Watermark (TFWM3 to TFWM0): These bits are used to make
threshold settings, which are used to set the TDRE bit in SISTR.
When the amount of primary send data in SITDR is less than or equal to the watermark setting, as
shown in the table below, the TDRE bit is set to 1.
Bit 3: TFWM3 Bit 2: TFWM2
0
0
1
1
0
1
Bit 1: TFWM1
0
1
0
1
0
1
0
1
Bit 0: TFWM0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Watermark setting
0
(Initial value)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Rev. 2.00 Mar 09, 2006 page 652 of 906
REJ09B0292-0200