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HD6417751 Datasheet, PDF (995/1105 Pages) Renesas Technology Corp – SuperH RISC engine
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Table 23.23 Clock and Control Signal Timing (HD6417751VF133)
VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = –20 to +75°C, CL = 30 pF
Item
Symbol
Min
Max
Unit Figure
EXTAL
clock input
frequency
PLL1/PLL2 1/2 divider
fEX
operating operating
1/2 divider not fEX
operating
30
45
MHz
15
23
PLL1/PLL2 1/2 divider
fEX
not operating operating
2
45
1/2 divider not fEX
operating
1
23
EXTAL clock input cycle time
tEXcyc
EXTAL clock input low-level pulse width
tEXL
EXTAL clock input high-level pulse width
tEXH
EXTAL clock output rise time
tEXr
EXTAL clock input fall time
tEXf
CKIO clock PLL2 operating
fOP
output
PLL2 not operating
fOP
CKIO clock output cycle time
tcyc
CKIO clock output low-level pulse width
tCKOL1
CKIO clock output high-level pulse width
tCKOH1
CKIO clock output rise time
tCKOr
CKIO clock output fall time
tCKOf
CKIO clock output low-level pulse width
tCKOL2
CKIO clock output high-level pulse width
tCKOH2
Power-on oscillation settling time
tOSC1
Power-on oscillation settling time/mode settling tOSCMD
MD reset setup time
tMDRS
MD reset hold time
tMDRH
#$% assert time
tRESW
22.2
1000 ns
23.1
3.5
—
ns
23.1
3.5
—
ns
23.1
—
4
ns
23.1
—
4
ns
23.1
30
67
MHz
1
67
MHz
14.9
1000 ns
23.2(1)
1
—
ns
23.2(1)
1
—
ns
23.2(1)
—
3
ns
23.2(1)
—
3
ns
23.2(1)
3
—
ns
23.2(2)
3
—
ns
23.2(2)
10
—
ms 23.3, 23.5
10
—
ms 23.3, 23.5
3
—
tcyc
20
—
ns
23.3, 23.5
20
—
tcyc
23.3, 23.4, 23.5,
23.6
PLL synchronization settling time
tPLL
200
—
µs
23.9, 23.10
Standby return oscillation settling time 1
tOSC2
10
—
ms 23.4, 23.6
Standby return oscillation settling time 2
tOSC3
5
—
ms 23.7
Standby return oscillation settling time 3
tOSC4
5
—
ms 23.8
IRL interrupt determination time
(RTC used, standby mode)
tIRLSTB
—
200
µs
23.10
%#$% reset hold time
tTRSTRH
0
—
ns
23.3, 23.5
Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 23 MHz.
When a 3rd overtone crystal resonator is used, an external tank circuit is necessary.
2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected
to the CKIO pin should be a maximum of 50 pF.
Rev. 3.0, 04/02, page 955 of 1064
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