HD6417751 Datasheet, PDF (657/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 15.16 shows an example of SCI operation for multiprocessor format reception.
1
Serial
data
Start
bit Data (ID1)
0 D0 D1
Stop Start Data
MPB _{bit bit (Data1)}
D7 1 1 0 D0 D1
Stop
MPB _bit
D7 0 1
1
Idle state
(mark state)
MPIE
RDRF
SCRDR1
value
ID1
RXI interrupt request
(multiprocessor
interrupt)
MPIE = 0
SCRDR1 data read
and RDRF flag
cleared to 0 by RXI
interrupt handler
As data is not
this station’s ID,
MPIE bit is set
to 1 again
RXI interrupt
request
The RDRF flag
is cleared to 0
by is the RXI
interrupt handler
(a) Data does not match station’s ID
1
Serial
data
Start
bit Data (ID2)
0 D0 D1
Stop Start Data
MPB _{bit bit (Data2)}
D7 1 1 0 D0 D1
Stop
MPB _bit
D7 0 1
1
Idle state
(mark state)
MPIE
RDRF
SCRDR1
value
ID1
ID2
Data2
RXI interrupt request
(multiprocessor interrupt)
MPIE = 0
SCRDR1 data read
and RDRF flag
cleared to 0 by RXI
interrupt handler
As data matches this
station’s ID, reception
continues and data is
received by RXI
interrupt handler
(b) Data matches station’s ID
MPIE bit set
to 1 again
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor
Bit, One Stop Bit)
Rev. 3.0, 04/02, page 617 of 1064