HD6417751 Datasheet, PDF (782/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt
request signal to the NMI pin is detected.
Bit 8: NMIE
0
1
Description
Interrupt request detected on falling edge of NMI input
Interrupt request detected on rising edge of NMI input
(Initial value)
Bit 7—IRL Pin Mode (IRLM): Specifies whether pins ,5/–,5/ are to be used as level-
encoded interrupt requests or as four independent interrupt requests.
Bit 7: IRLM
0
1
Description
,5/ pins used as level-encoded interrupt requests
(Initial value)
,5/ pins used as four independent interrupt requests (level-sense IRQ
mode)
Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written
with 0.
19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00)
The interrupt priority level setting register (INTPRI00) sets the order of priority (levels 15 to 0) of
the internal peripheral module interrupts. The INTPRI00 register is a 32-bit read/write register. It
is initialized to H'00000000 at a reset. It is not initialized in standby mode.
Bit: 31
30
29
...
19
18
17
16
...
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
...
3
2
1
0
...
Initial value: 0
0
0
...
0
0
0
0
R/W: R/W
R/W
R/W
...
R/W
R/W
R/W
R/W
Table 19.6 shows the relationship between interrupt request sources and the respective bits of the
INTPRI00 register.
Rev. 3.0, 04/02, page 742 of 1064