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HD6417751 Datasheet, PDF (94/1105 Pages) Renesas Technology Corp – SuperH RISC engine
3.1.3 Register Configuration
The MMU registers are shown in table 3.1.
Table 3.1 MMU Registers
Name
Abbrevia-
Initial
tion
R/W Value*1
P4
Address*2
Area 7
Address*2
Access
Size
Page table entry high
register
PTEH
R/W Undefined H'FF00 0000 H'1F00 0000 32
Page table entry low
register
PTEL
R/W Undefined H'FF00 0004 H'1F00 0004 32
Page table entry
assistance register
PTEA
R/W Undefined H'FF00 0034 H'1F00 0034 32
Translation table base TTB
register
R/W Undefined H'FF00 0008 H'1F00 0008 32
TLB exception address TEA
register
R/W Undefined H'FF00 000C H'1F00 000C 32
MMU control register MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32
Notes: *1 The initial value is the value after a power-on reset or manual reset.
*2 P4 address is the address when using the virtual/physical address space P4 area. The
area 7 address is the address used when making an access from physical address
space area 7 using the TLB.
3.1.4 Caution
Operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
Rev. 3.0, 04/02, page 54 of 1064