HD6417751 Datasheet, PDF (383/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles
inserted in the setup time from the address until assertion of the read/write strobe. Valid only for
SRAM interface, byte control SRAM interface, and burst ROM interface:
Bit 4n + 2: AnS0
0
1
Waits Inserted in Setup
0
1
(Initial value)
(n = 6 to 0)
Bits 4n + 1 and 4n—Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits
specify the number of cycles to be inserted in the hold time from negation of the write strobe.
When reading, they specify the number of cycles to be inserted in the hold time from the data
sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM
interface:
Bit 4n + 1: AnH1
0
1
Bit 4n: AnH0
0
1
0
1
Waits Inserted in Hold
0
1
2
3
(Initial value)
(n = 6 to 0)
Bits 4n+3Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in
the SH7751R): When reading, these bits specify the timing for the negation of read strobe. These
bits should be cleared to 0 when a byte control SRAM setting is made. When reading in area 1 or
4, AnRDH bits specify the number of cycles to be inserted in the hold time from the time at which
the data is sampled or from the negation of the read strobe. Valid only for the SRAM interface.
Bit 4n + 3: AnRDH
0
1
Waits Inserted in Hold
0
1
(Initial value)
Rev. 3.0, 04/02, page 343 of 1064