HD6417751 Datasheet, PDF (733/1105 Pages) Renesas Technology Corp – SuperH RISC engine

The bit rate error is given by the following equation:
Pφ
Error (%) = _{1488 × 22n–1 × B × (N + 1)} × 10⁶ – 1 × 100
Table 17.8 shows the relationship between the smart card interface transmit/receive clock register
settings and the output state.
Table 17.8 Register Settings and SCK Pin State
Register Values
SCK Pin
Setting SMIF GM
1*¹
1
0
CKE1 CKE0
0
0
Output
Port
State
Determined by setting of SPB1IO
and SPB1DT bits in SCSPTR1
1
0
0
1
SCK (serial clock) output state
2*²
1
1
0
0
Low output Low-level output state
1
1
0
1
SCK (serial clock) output state
3*²
1
1
1
0
High output High-level output state
1
1
1
1
SCK (serial clock) output state
Notes: *1 The SCK output state changes as soon as the CKE0 bit setting is changed.
Clear the CKE1 bit to 0.
*2 Stopping and starting the clock by changing the CKE0 bit setting does not affect the
clock duty cycle.
Port value ^{Width is}
undefined
SCK
Width is
undefined Port value
CKE1 value
Specified
width
SCK
(a) When GM = 0
Specified
width
CKE1 value
(b) When GM = 1
Figure 17.6 Difference in Clock Output According to GM Bit Setting
Rev. 3.0, 04/02, page 693 of 1064